![]() I'm doing this to get used to the whole process before I actually work on it.ītw I made a frequency divider using JK flipflops and that worked fine on both, the cpld and ModelSim simulation. ![]() I've been stuck on this for a while now and really need it to work because I'll be needing ModelSim to make programs for some upcoming projects. I've tried a lot of different things that I've read from different forums such as trying to run it without a testbench by giving a Clock input directly in ModelSim, trying reg outputs instead of wires and vice versa, amongst other things. Then I wrote A testbench to simulate a clock input for the LPM_counter module. However when I try to simulate it in ModelSim it gives 'z' (high impedance) on all outputs.įor the simulation I created a Verilog file from the BDF file using the 'Create HDL design file fron current file' option in Quartus. ![]() I wrote a program in Block schematic format (BDF) adn downloaded it into the cpld and it works fine, giving the desired output. ![]() I'm trying to implement a simple 9-bit frequency divider using the LPM_counter Module. ![]()
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